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565РУ7, КР565РУ7В, КР565РУ7Г, КР565РУ7Д, КР565РУ7И, КР565РУ7К, КР565РУ7Л, КР565РУ7Д1, КР565РУ7Д2


Dynamic operational storage (DRAM) chips device with a capacity of 262144 bit (256kbit x 1). Chips used semiconductor technology on n-channel MOS transistors. Contains 569466 integral elements. Package type 238.16-1, weight not more than 1.2 g and 2103.16-13.01.

Условное графическое обозначение К565РУ7, КР565РУ7

Pin assignment

1 - address input A8
2 - information input DI
Z - input signal recording WR
4 - input of the RAS row selection signal
5 - address input A0
6 - address input A2
7 - address input A1
8 - supply voltage
9 - address input A7
10 - address input A5
11 - address input A4
12 - address input A3
13 - address input A6
14 - information output D0
15 - input signal selection columns CAS
16 - common

Truth table

Inputs Output State
1 1 Any Any High impedance Chip not selected
1 0 Any Any High impedance Chip not selected
0 1 Any Any High impedance Regeneration
0 0 0 0 or 1 High impedance Write 0 or 1
0 0 1 Any 0 or 1 Reading

К565РУ7, КР565РУ7 structure circuit

The storage is organized in the form of a matrix containing 512 rows and 512 columns. In addition, IC includes two dual row quads of spare rows and four pairs of spare columns, for a total of 8,256 spare cells.

The memory control circuit consists of two clock signal generators, which are activated by the RAS# (row address strobe) and CAS# (column address strobe) signals. To access any of the memory cells, an 18-bit code is applied to the 9-bit address register in multiplex mode -

  • First, the least significant nine bits of the address are supplied in the parallel code, which are used to fetch the desired line,
  • The row address code is fixed on the address register using the RAS# signal when it goes to the lower logical level,
  • Then the nine most significant bits of the address code corresponding to the column address are supplied to the same pins,
  • The column address code is latched onto the address register using a second clock signal, CAS#.

The chip marking codes are as follows:

  • the letter <В> is encoded with two dots (..),
  • the letter <Г> is encoded with three dots (:),
  • the letter <Д> is not highlighted with dots on the body.

The microcircuits are not analogous to 41256 due to a different regeneration scheme and the absence of Page Mode.

Recommendations for use

Permissible value of static potential is 100 V. After wiring ICs with the boards must be varnished with UR-2Z1 or EP-780 in no less than 3 layers.



1. The dynamic current consumption corresponds to the set value at a cycle time of ≥ 340 ns (KR565RU78), ≥ 410 ns (KR565RU7G), ≥ 500 ns (KR565RU7D, KR565RU7D1, KR565RU7D2).

2. Regeneration is performed in during 512 cycles.


Power dissipation
<350 mW
IC package
201.16-17, 238.16-1, 2104.18-1, 201.9-1
IC manufacture technology
IC series
Logic gate family
Query time
<150 ns<200 ns<250 ns<150 ns<200 ns<250 ns<250 ns<250 ns
Memory organization
256k x 1256k x 1256k x 1256k x 1256k x 1256k x 1128k x 1128k x 1